1. Field of the Invention
This invention generally relates to methods and systems for generating a wafer inspection process using bit failures and virtual inspection.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
Some inspection recipes (or a set of instructions used to perform an inspection process) have been generated based on known defects of interest (DOIs). For example, inspection recipes can be set up so that they detect as many DOIs as possible while not detecting other defects not of interest, nuisance, and noise. One problem in setting up inspection recipes in this manner is that it is not always possible to know which DOIs will be killer defects and cause a device to fail. For example, there is currently no simple way to verify if a defect is a killer defect. A user may guess if a defect is a killer defect based on its characteristics such size, classification, and location and based on the defect-related experience of the user. However, the user may not be able to predict which defects will be killer defects with any degree of accuracy or precision. Therefore, it is not always easy or even possible to set up inspection recipes to detect the defects of most interest, killer defects.
Accordingly, it would be advantageous to develop systems and/or methods for generating a wafer inspection process that do not have one or more of the disadvantages described above.